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AD7725 16-bit sigma-delta adc with programmable postprocessor rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective companies. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ? 2003 analog devices, inc. all rights reserved. features programmable filtering: any characteristic up to 108 tap fir and/or iir polynomial signal conditioning up to 8 th order programmable decimation and output word rate flexible programming modes: boot from dsp or external eprom parallel/serial interface internal default filter for evaluation 14.4 mhz max master clock frequency 0 v to +4 v (single-ended) or 2 v (differential) input range power supplies: av dd , dv dd : 5 v 5% on-chip 2.5 v voltage reference 44-lead mqfp package typical applications radar sonar auxiliary car functions medical communications functional block diagram general description the AD7725 is a complete 16-bit, sigma-delta analog-to-digital converter with on-chip, user-programmable signal conditioning. the output of the modulator is processed by three cascaded finite impulse response (fir) filters, followed by a fully user- programmable postprocessor. the postprocessor provides processing power of up to 130 million accumulates (mac) per second. the user has complete control over the filter response, the filter coefficients, and the decimation ratio. the postprocessor permits the signal conditioning characteristics to be programmed through a parallel or serial interface. it is programmed by loading a user-defined filter in the form of a configuration file. this filter can be loaded from a dsp or an external serial eprom. it is generated using a digital filter design package called filter wizard, which is available from th e AD7725 section on the analog devices website. f ilter wiz- ard allows the user t o design different filter types and gener- ates the appropriate configuration file to be downloaded to the postprocessor. the AD7725 also has an internal default filter for evaluation purposes. it provides 16-bit performance for input bandwidths up to 350 khz with an output word rate of 900 khz maximum. the input sample rate is set either by the crystal oscillator or an external clock. this part has an accurate on-chip 2.5 v reference for the modu- lator. a reference input/output function is provided to allow either the internal reference or an external system reference to be used as the reference source for the modulator. the device is available in a 44-lead mqfp package and is specified over a 40 o c to +85 o c temperature range. 2.5v reference post- processor default filter (rom ) xtal clock preset filter mod control logic uni half pwr stby sync s/ p v in (+) v in (? rd/ wr soe / cs cfmt/rs dval / int sdi/db0 err / db1 db2 db3 resetcfg / db4 int/db5 fsi/db6 sco/db7 sdo/db8 scr/db13 cfgend/db12 db11 db10 fso/db9 smode1/db15 smode0/db14 xtal_off xtal clkin dv dd dgnd ref2 ref1 av dd a gnd AD7725
rev. 0 e2e AD7725especifications 1 (av dd = 5 v 5%, agnd = agnd1 = agnd2 = dgnd = 0 v, f clkin 2 = 9.6 mhz, ref2 = 2.5 v, t a = t min to t max , unless otherwise noted.) b version parameter test conditions/comments min typ max unit dynamic specifications when tested with the fir filter in figure 1. half_pwr = logic high bipolar mode signal to noise 3 measurement bandwidth = 0.5 ? = ?
rev. 0 AD7725 e3e b version parameter test conditions/comments min typ max unit all logic inputs i in , input current v in = 0 v to dv dd = = = + = = = = = = =
rev. 0 e4e AD7725 preset filter, default filter, and postprocessor characteristics 1, 2 parameter test conditions/comments min typ max unit digital filter response preset fir data output rate f clkin /8 hz stop-band attenuation 70 db low-pass corner frequency f clkin /16 hz group delay 3 133/(2
rev. 0 AD7725 e5e parameter symbol min typ max unit clkin frequency f clkin 114. 4 mhz clkin period (t clk = 1/f clkin )t 1 0.07 1 soe l f sco r e cl d s sco r e parallel terface data wrte rs l cs l wr s cs l rs cs r e cs p wr cs r e d s t d t data read rs l cs l rd s cs l rs cs r e rd cs r e d v cs falling edge 3 t 31 30 ns data hold after cs r e stats readstrcto wrte cs d c cl c cs l rd s cs l rd cs r e r d a t r d cs r e w d s cs r e w d cs r e otes g s = = = =
rev. 0 e6e AD7725 c l 25pf i oh 200 a i ol 1.6ma 1.6v to output pin figure 2. load circuit for digital output timing specifications t 5 clkin sco scr = 0 sco scr = 1 2.3v 0.8v t 4 t 1 t 3 t 2 t 6 t 7 t 6 t 7 figure 3. clkin to sco relationship sdo sco cfmt = 0 t 8 t 9 t 12 t 13 t 15 t 14 t 10 t 11 fso sdi fsi d15 d0 d15 d4 d3 d2 d1 d15 d14 d13 d12 d1 d0 d15 d14 d4 d2 d3 d1 figure 4. serial mode (dsp mode and boot from rom (bfr) mode). in bfr mode, fsi and sdi are not used.
rev. 0 AD7725 e7e t 19 sco soe t 18 sdi t 16 t 1 7 figure 5. serial mode (eprom mode) t 25 t 21 db0 db15 e t 22 t 23 t 24 int rs t 26 20 t three-state three-state valid data cs rd/ wr figure 6. parallel mode (writing data to the AD7725) three-state three-state t 28 t 27 t 30 t 29 t 32 t 23 t 31 db0 db15 e int rs va l id data cs rd/ wr figure 7. parallel mode (reading data to the AD7725)
rev. 0 e8e AD7725 absolute maximum ratings 1 (t a = 25 c, unless otherwise noted.) dv dd to dgnd . . . . . . . . . . . . . . . . . . . . . . . . e0.3 v to +7 v av dd to agnd . . . . . . . . . . . . . . . . . . . . . . . . . e0.3 v to +7 v av dd , av dd1 to dv dd . . . . . . . . . . . . . . . . . . . . e1 v to +1 v agnd, agnd1 to dgnd . . . . . . . . . . . . . e0.3 v to +0.3 v digital inputs to dgnd . . . . . . . . . . e0.3 v to dv dd + 0.3 v digital outputs to dgnd . . . . . . . . . e0.3 v to dv dd + 0.3 v v in (+), v in (e) to agnd . . . . . . . . . . . e0.3 v to av dd + 0.3 v ref1 to agnd . . . . . . . . . . . . . . . . . e0.3 v to av dd + 0.3 v ref2 to agnd . . . . . . . . . . . . . . . . . e0.3 v to av dd + 0.3 v refin to agnd . . . . . . . . . . . . . . . . e0.3 v to av dd + 0.3 v dgnd, agnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 v input current to any pin except supplies 2 . . . . . . . . . 10 ma i dd (ai dd + di dd ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 ma operating temperature range . . . . . . . . . . . . e40 c to +85 c storage temperature range . . . . . . . . . . . . . e65 c to +150 c junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150 c ja thermal impedance . . . . . . . . . . . . . . . . . . . . . . . . 58 c/w jc thermal impedance . . . . . . . . . . . . . . . . . . . . . . . . 20 c/w lead temperature, soldering vapor phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . 215 c infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 c esd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 kv notes 1 stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 transient currents of up to 100 ma will not cause scr latch-up. ordering guide temperature package package model range description option 1 AD7725bs e40 c to +85 c plastic quad s-44 flatpack eval- evaluation AD7725cb 2 board eval- controller control board brd2 3 1 s = plastic quad flatpack (mqfp) 2 this board can be used as a standalone evaluation board or in conjunction with the evaluation board controller for evaluation/demonstration purposes. it is accom- panied by software and technical documentation. 3 evaluation board controller. this board is a complete unit allowing a pc to control and communicate with all analog devices boards ending in the cb designator. to obtain the complete evaluation kit, the following needs to be ordered: eval-AD7725cb, eval-control brd2, and a 12 v ac transformer. the filter wizard software can be downloaded from the analog devices website. caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the AD7725 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. s t a t u s i n s t ruc t i on db0 db15 e int rs cs rd/ wr t 34 t 33 t 40 t 36 t 35 t 38 t 23 t 37 t 39 three-state three-state three-state figure 8. parallel mode (reading the status register and writing instructions)
rev. 0 AD7725 e9e pin configuration 3 4 5 6 7 1 2 10 11 8 9 40 39 38 41 42 43 44 36 35 34 37 29 30 31 32 33 27 28 25 26 23 24 pin 1 identifier top view (not to scale) 12 13 14 15 16 17 18 19 20 21 22 scr/db13 smode0/db14 smode1/db15 soe / cs sync dgnd stby AD7725 clkin efmt/db2 err /db1 sdi/db0 cfmt/rs dval /int dgnd rd/ wr s/ p agnd1 agnd1 av dd1 av dd agnd uni ref2 dgnd/db3 fsi/db6 sco/db7 dv dd sdo/db8 fso/db9 xtal xtaloff half_pwr agnd av dd agnd v in ( e ) v in ( + ) ref1 agnd2 resetcfg /db4 init/db5 dgnd/db10 dgnd/db11 cfgend/db12 pin function description pin no. mnemonic s/p description 1 efmt/db2 serial mode . efmteserial clock format, logic input. this clock format pin selects the clock edge to be used during configuration. when efmt is low, serial data in is valid on the rising edge of sco; when efmt is high, serial data in is valid on the falling edge of sco. during normal operation, this pin is ignored. parallel mode . db2edata input/output bit. 2 err d s err configuration error flag, logic output. if an error occurs during configuration, this output goes low and is reset high by a pulse on the resetcfg p dd o sdd s sds d s ad s sco p dd o ls cftrs s cfts c f l t w cft s d o sco cft s d o sco d p rsr s rs w rs s r ad w rs adc d ad t
rev. 0 e10e AD7725 pin no. mnemonic s/p description 5 dval t s dval d v l o t p t l o t a t a w w w r r a d crc r s r t r s r dgd g r d c rd wr s t s dgd p rw l t cs a rd wr a rd wr t cs s p sp s w s p p s s p t agd d l p s g a av dd d l p s a cl c a taloff a
rev. 0 AD7725 e11e pin no. mnemonic s/p description 27 stby standby, logic input. when stby is taken high, the device will enter a low power mode. if the device was fully configured before entering this mode, it will not lose its configu- ration data. when stby is brought low, the device exits the low power mode. if the device was partly configured before entering the low power mode, it will restart the configuration process in the case of boot from rom (bfr) mode, dsp mode, and eprom mode or, in parallel mode, a new configure instruction must be issued to configure the device. if the device was fully configured before entering the low power mode, it will continue to output conversion results in all serial modes; in parallel mode, the device will wait for an instruction to begin converting. in stby mode, the clock input must be continual. 28 dgnd ground reference for digital circuitry 29 sync synchronization logic input. when using more than one AD7725 operated from a common master clock, sync allows each adc to simultaneously sample its analog input and update its output register. when sync is high, the digital filter sequencer counter is reset to zero and the postprocessor core is reset. because the digital filter and sequencer are completely reset during this action, sync pulses cannot be applied continuously. when sync is taken low, normal conversions continue, with valid data resulting after the filter setting time. 30 soe cs s soe s o e epro soe epro epro dsp soe is an active high interrupt. it goes high after a power on reset and after a pulse on the resetcfg soe fs cl fr soe cl p cs c s l t rd wr f r cs rs f w cs rs ad cs soded s sodes s l t t v t p dd o s soded s sodes s l t t v t p dd o scrd s scrs c r s l w scr sco cl a sco cl p dd o cfgedd s cfgedc e l o a cfged p dd o dgdd s dgdd g p dd o dgdd s dgdd g p dd o fsod s fsof s o fso sdo t fso sco p dd o
rev. 0 e12e AD7725 pin no. mnemonic s/p description 38 sdo/db8 serial mode . sdoeserial data output. the serial data is shifted out of the AD7725 msb first, in twos complement format, synchronous with sco. parallel mode . db8edata input/output bit. 39 dv dd digital power supply voltage 40 sco/db7 serial mode . scoeserial clock output. the frequency of sco is a function of the clkin frequency and is set by the scr pin. parallel mode . db7edata input/output bit. 41 fsi/db6 serial mode . fsieframe synchronization input. fsi indicates the beginning of a word transmission on the sdi pin. parallel mode . db6edata input/output bit. 42 init/db5 serial mode . initelogic input. when the device is correctly configured, a logic low on this pin will prevent the device from converting. when this pin is taken high, the device will start converting. when daisy-chaining multiple devices, this pin ensures that all devices sample their analog inputs simultaneously without needing to activate the sync pin. parallel mode . db5edata input/output bit. 43 resetcfg d s resetcfg l resetcfg a t soe resetcfg pin and then again following a successful configuration. parallel mode . db4?ata input/output bit. 44 dgnd/db3 serial mode . dgnd?igital ground. parallel mode . db3?ata input/output bit.
rev. 0 AD7725 e13e terminology integral nonlinearity (inl) this is the maximum deviation of any code from a straight line passing through the endpoints of the transfer function. the endpoints of the transfer function are zero scale (not to be confused with bipolar zero), a point 0.5 lsb below the first code transition (100 . . . 00 to 100 . . . 01 in bipolar mode, 000 . . . 00 to 000 . . . 01 in unipolar mode) and full scale, a point 0.5 lsb above the last code transition (011 . . . 10 to 011 . . . 11 in bipolar mode, 111 . . . 10 to 111 . . . 11 in unipolar mode). the error is expressed in lsbs. differential nonlinearity (dnl) this is the difference between the measured and the ideal 1l sb change between two adjacent codes in the adc. unipolar offset error unipolar offset error is the deviation of the first code transition from the ideal v in (+) voltage, which is (v in (e) + 0.5 lsb) when operating in the unipolar mode. bipolar offset error this is the deviation of the midscale transition code (111 . . . 11 to 000 . . . 00) from the ideal v in (+) voltage, which is (v in (e) e 0.5 lsb) when operating in the bipolar mode. gain error the first code transition should occur at an analog value 0.5 lsb above negative full scale. the last code transition should occur for an analog value 1.5 lsb below the nominal full scale. gain error is the deviation of the actual difference between first and last code transitions and the ideal difference between first and last code transitions. signal-to-noise snr is the measured signal-to-noise ratio at the output of the adc. the signal is the rms magnitude of the fundamental. noise is the rms sum of all of the nonfundamental signals up to half the output data rate (f o /2), excluding dc. the adc is evaluated by applying a low noise, low distortion sine wave signal to the input pins. by generating a fast fourier trans- form (fft) plot, the snr data can then be obtained from the output spectrum. total harmonic distortion (thd) thd is the ratio of the rms sum of the harmonics to the rms value of the fundamental. thd is defined as: thd vvvvv v = ++++ ? ? ? ? ? ? ? ? v 1 is the rms amplitude of the fundamental and v 2 , v 3 , v 4 , v 5 , and v 6 are the rms amplitudes of the second through sixth harmonics. spurious free dynamic range (sfdr) defined as the difference, in db, between the peak spurious or harmonic component in the adc output spectrum (up to f o /2 and excluding dc) and the rms value of the fundamental. normally, the value of this specification will be determined by the largest harmonic in the output spectrum of the fft. for input signals whose second harmonics occur in the stop band region of the digital filter, the spur in the noise floor limits the sfdr. setting time and group delay the settling time of a digital filter is dependent on the amount of decimation employed and the number of filter taps used in the filter design and is calculated as follows: settling time data input rate number of taps = ? ? ? ? ? ?
rev. 0 e14e AD7725etypical performance characteristics performance plots the following typical plots are generated using the digital filter shown in figure 1. (av dd = dv dd , t a = 25
rev. 0 AD7725 e15e circuit description the AD7725 employs a sigma-delta conversion technique to convert the analog input into an equivalent digital word. the modulator samples the input waveform and outputs an equiva- lent digital word at the input clock frequency, f clkin . due to the high oversampling rate, which spreads the quantiza- tion noise from 0 to f clkin /2, the noise energy contained in the band of interest is reduced (figure 9a). to further reduce the quantization noise, a high order modulator is employed to shape the noise spectrum so that most of the noise energy is shifted out of the band of interest (figure 9b). the digital filtering that follows the modulator removes the large out-of-band quantization noise (figure 9c) while also reducing the data rate from f clkin at the input of the filter to f clkin /16 or less at the output of the filter, depending on the filter type used. digital filtering has certain advantages over analog filtering. since digital filtering occurs after the a/d conversion, it can remove noise injected during the conversion process. analog filtering cannot do this. the digital filter also has a linear phase response. a. b. c. qu antization noise noise shaping digital filter cutoff frequency f clkin /2 f clkin /2 f clkin /2 b and of interest b and of interest b and of interest figure 9. sigma-delta adc the AD7725 employs three fixed finite impulse response (fir) filters in series. each individual filter?s output data rate is half that of its input data rate. the fourth stage is programmable, with the user being able to select a range of different filter responses. both the filter response and the decimation are user program- mable. see the filtering section for more details. applying the AD7725 analog input range the AD7725 has differential inputs to provide common-mode noise rejection. in unipolar mode, the analog input is single- ended and its range is 0 v to (8/5 + ? ? ? ?
rev. 0 e16e AD7725 a b a b 500 500 ac ground clkin a a b b 2pf 2pf v in (+) v in (e) AD7725 figure 11. analog input equivalent circuit driving the analog inputs to interface the signal source to the AD7725, at least one op amp will generally be required. the choice of op amp will be critical to achieving the full performance of the AD7725. the op amp not only has to recover from the transient loads that the adc imposes on it, but it must also have good distortion char- acteristics and very low input noise. resistors in the signal path will also add to the overall thermal noise floor, necessitating the choice of low value resistors. placing an rc filter between the drive source and the adc inputs, as shown in figure 12, has a number of beneficial effects: tran- sients on the op amp outputs are significantly reduced since the external capacitor now supplies the instantaneous charge required when the sampling capacitors are switched to the adc input pins, and input circuit noise at the sample images is now signifi- cantly attenuated, resulting in improved overall snr. the external resistor serves to isolate the external capacitor from the adc output, thus improving op amp stability while also isolating the op amp output from any remaining transients on the capacitor. by experimenting with different filter values, the optimum perfor- mance can be achieved for each application. as a guideline, the rc time constant (r
rev. 0 AD7725 e17e 220pf AD7725 v in (+) v in (e) 27 r in 390 10k 10nf 220nf 1 f 27 220 ain = 2v biased about ground ref2 ref1 r fb 220 r source 20k 220 220 50 figure 14. single-ended-to-differential input circuit for bipolar mode operation (analog input biased about ground) applying the reference the AD7725 can operate with either an external reference or with its on-chip 2.5 v reference. a block diagram of the internal reference circuit is shown in f igure 15. the internal reference circuitry includes an on-chip 2.5 v band gap reference and a reference buffer circuit. the internal 2.5 v reference voltage is connected to the ref1 pin through a 3 k ? ? ? ? ? ? ? ? ? ? ? = + ? ?
rev. 0 e18e AD7725 xtal mclk 1m figure 18. crystal oscillator connection when an external clock source is being used, the internal oscil- lator circuit can be disabled by tying xtal_off high. a low phase noise clock should be used to generate the adc sam- pling clock because sampling clock jitter effectively modulates the i nput signal and raises the noise floor. the sampling clock generator should be isolated from noisy digital circuits, grounded, and heavily decoupled to the analog ground plane. the sampling clock generator should be referenced to the analog ground in a split ground system. however, this is not always pos- sible because of system constraints. in many applications, the sampling clock must be derived from a higher frequency multi- purpose system clock that is generated on the digital ground plane. if the clock signal is passed between its origin on a digital ground plane to the AD7725 on the analog ground plane, the ground noise between the two planes adds directly to the clock and will produce excess jitter. the jitter can cause degradation in the signal-to-noise ratio and also produce unwanted harmon- ics. this can be remedied somewhat by transmitting the sampling signal as a differential one, using either a small rf transformer or a high speed differential driver and a receiver such as pecl. in either case, the original master system clock should be gener- ated from a low phase noise crystal oscillator. system synchronization the sync input provides a synchronization function for use in parallel or serial mode. sync allows the user to begin gather- ing samples of the analog input from a known point in time. t his allows a system using multiple AD7725s, operated from a common master clock, to be synchronized so that each adc simultaneously updates its output register. in a system using multiple AD7725s, a common signal to their sync inputs will synchronize their operation. when sync is high, the digital filter sequencer is reset to zero. a sync pulse, one clkin cycle long, can be applied. this way, sync is sensed low on the next rising edge of clkin. when sync is sensed low, normal conversion continues. following a sync, the modulator and filter need time to settle before data can be read from the AD7725. also, when init is taken high, it activates sync, which ensures that multiple devices cascaded in serial mode will sample their analog inputs simultaneously. filtering the preset filter the preset filter is the digital filter directly following the modu- lator. this is a fixed filter whose main function is to remove the large out-of-band quantization noise shaped by the modulator. this filter is made up of three cascaded half-band fir filters, and each filter decimates by two. the word rate into the preset filter is clkin, and due to the decimation in the three subse- quent filter stages, the output word rate of the preset filter, and thus the input word rate to the postprocessor, is clkin/8. see figure 19. post- p rocessor modulator fir 1 dec 2 fir 2 dec 2 fir 3 dec 2 pr eset filter input word rate = clkin ou tput word rate = clkin/8 figure 19. the preset filter the postprocessor the AD7725 contains systolix?s pulsedsp tm user-program- mable postprocessor. the postprocessor directly follows the preset filter. the postprocessor core is a systolic array of simple high performance processors. these processors are grouped into 36 multiply accumulate (mac) blocks, with each block con- sisting of three multipliers and one adder. each block can process three filter taps, thus the postprocessor allows up to 36
rev. 0 AD7725 e19e output word rate. the AD7725 postprocessor supports decima- tion/interpolation by factors up to 256. figure 20 shows an example of a filtering function implemented on the postprocessor. figure 20a shows the data path representa- tion of an fir filter, while figure 20b shows how this algorithm would be implemented on the AD7725. because the postprocessor can implement three filter taps per mac block, 1.3 mac blocks are required to implement a 4-tap fir filter. this is a useful guideline when calculating the design requirements for a new application. signal in z e1 c 0 signal out c 1 c 2 c 3 z e1 z e1 z e1 a) fir data path representation signal in signal out c 1 c 2 c 3 z e1 z e1 c 0 z e1 z e1 z e1 1 mac block b) fir postprocessor implementation figure 20. AD7725 postprocessor mapping programming the postprocessor the postprocessor is programmed by loading a user-defined filter in the form of a configuration file into the device. generating a configuration file to load into the postprocessor a user-defined configuration file can be generated to load into the postprocessor on the AD7725 to program the multipliers and accumulators to perform user-specific filtering require- ments. the configuration file can be generated using a digital filter design package called filter wizard, which is available from the analog devices website. filter wizard this digital filter design package allows the user to design differ- ent filter types and then generates the appropriate configuration file to be loaded into the postprocessor. this application includes the ability to specify a range of different filter options including single or multistage; normalized or user-specified output fre- quency; fir or iir; low-pass, band-pass; window type; pass-band frequency and ripple; stop-band frequency, attenua- tion and ripple; daisy-chaining and interlacing. it also informs the user of the power dissipation of the AD7725 associated with the particular filter designed. this is to avoid filters being designed that result in the device exceeding its maximum power specifica- tions. the magnitude, phase, and impulse responses can be plotted so that the user knows the filter response (cutoff fre- quency, transition width, attenuation) before generating the coefficients. once the filter characteristics have been decided, the configuration file is generated and will be ready for loading into the postprocessor. filter configuration file format the configuration file that is generated by the filter wizard is made up of 8272 bits of data. the first word in the file is called the id word, and the device will only accept the configuration file if this is 0x7725. the rest of the configuration data is split into 12 blocks of 672 bits. the AD7725 postprocessor therefore accepts 672 bits at a time (42, 16-bit words). each block of 672 bits is followed by a cyclic redundancy check (crc) word. the id word and the crc words are used by the device to check for errors in the configuration file and are not actually written to the postprocessor. the postprocessor therefore holds 8064 bits of data (672 + =
rev. 0 e20e AD7725 filter design the bit stream of data from the modulator and preset filter is available to the postprocessor at a frequency of clkin/8. due to the nature of the design of the postprocessor, there is an unavoidable minimum decimate by two resulting in the maxi- mum output data rate of any filter being clkin/16. a filter can be either fir or iir in design. fir filters are inher- ently stable and have linear phase. however, they are computationally in efficient and require more coefficients for a given roll-off com- pared to iir filters. iir filters have the disadvantage of being potentially unstable and having nonlinear phase. the maximum number of taps that the postprocessor can hold is 108. therefore, a single filter with 108 taps can be generated, or a multistage filter can be designed whereby the total number of taps adds up to 108. design factors (i)stop-band attenuation and transition width in filter design, it is desirable to have a large stop-band attenua- tion and a narrow filter transition width. to achieve both of these, a large number of filter taps is required. therefore some compromises have to be made during the design to be able to optimize the amount of taps used. there is usually a trade-off of stop-band attenuation for transition width, or vice versa. for ex- ample, a filter with a cutoff frequency of 100 khz that rolls off between 100 khz and 200 khz uses fewer taps than a filter with a cutoff frequency of 100 khz that rolls off between 100 khz and 150 khz. to reduce the number of taps used to achieve a certain specification, a multistage filter can be designed that performs decimation between stages. the first filter stage can be used to perform decimation and as a prefilter to remove out-of-band noise, then the subsequent stages can have more stringent specifications. (ii)decimation decimation reduces the output data rate of the filter, resulting in lower input data rates for subsequent filter stages. when decimation is used in a multistage filter, the noise is wrapped around f s /2 each time the bit stream is decimated by two. it is therefore important to appropriately filter out the quantization noise that will wrap into the band of interest when decimation occurs, prior to decimation. with appropriate filtering, the noise floor will increase by 3 db each time the data stream is decimated by two; however the noise floor is down at 120 db prior to decimation. therefore, with suitable deci- mation, the snr will be 83 db typically at the AD7725 output. decimating the data rate allows an improvement in the filter transition width equal to the inverse of the decimation factor. for fir filters, if a filter is designed for an input data rate of half the maximum data rate, i.e., the previous filter stage had decimation by two, the filter can obtain half the transition width of a filter designed for the maximum input data rate for a given number of taps. for example, the number of taps required to generate a filter with a cutoff frequency of 100 khz and a stop-band frequency of 200 khz will equal the number of taps required to generate a filter with a cutoff frequency of 100 khz and a stop-band frequency of 150 khz if the data stream is deci mated by two prior to the filtering stage. for iir filters, decimation has no effect on the transition width. when decimation is performed, the amount of filter coefficients required to achieve certain filter specifications is reduced, result- ing in a reduction in the power dissipation of the device to realize the filter. therefore, if a one-stage filter meets the roll-off and stop-band attenuation requirements of the application but is dissipating more power than is acceptable, then decimation will provide a solution here. prior to decimating, a suggestion is to use a half-band filter as these require a low number of taps to accomplish simple low-pass filtering. a half-band filter has its midpoint of the transition region centered on half the nyquist frequency (or f s /4). by decimating though, because the input to subsequent stages is reduced, so is the bandwidth. figure 22 shows that for a given transition width, as the decimation factor prior to the filter is increased the current consumption is reduced, resulting in reduced power dissipation. decimation factor 120 100 40 08 2 i dd ?ma 46 80 60 figure 22. i dd vs. decimation for a filter with a transition width of 66 khz as shown in figure 1 power consumption vs. filter taps vs. clkin frequency when designing filters for the AD7725, an important factor to take into account is the power consumption. there is a direct relationship between di dd , the number of filter taps used in the postprocessor, and the clkin frequency. the maximum i dd (combined ai dd a nd di dd ) allowed by the AD7725 pack- age is 150 ma. the more filter taps used, the higher the di dd . also, the higher the clkin frequency, the higher the di dd . therefore, a trade-off sometimes needs to be made between clkin frequency and filter taps to stay within the power budget of the part. these power constraints are built into the filter design package, filter wizard. as the filter is being designed, the power con- sumption is shown and is highlighted once the power budget has been exceeded.
rev. 0 AD7725 e21e figures 23 and 24 show plots of filter taps and clkin frequency versus i dd . clkin e mhz 180 140 0 0 14.4 i dd e ma 100 40 2.4 4.8 7.2 9.6 12 120 60 20 160 80 maximum i dd 72taps 54taps half_pwr disabled half_pwr enabled 90taps 108taps 36taps figure 23. typical i dd vs. clkin for various numbers of filter taps to get a more accurate number of taps for a given clkin frequency, see figure 24. filter taps 180 140 0 0 100 10 i dd e ma 100 40 20 30 40 50 60 70 80 90 120 60 20 160 80 maximum i dd 14.4mhz 12mhz 9.6mhz 7.2mhz 4.8mhz 2.4mhz 1mhz 110 figure 24. typical i dd vs. filter taps for various clkin frequencies figures 23 and 24 were done for a 1-stage low-pass fir filter, which will give the worst case i dd figures. the i dd will decrease as the amount of decimation employed in the filter is increased. modes of operation the AD7725 can operate with either a serial or a parallel interface. these modes are chosen by setting the logic state of the s/ p parallel ode t p s p dgd p ad p t t f ad dsp f ad s p sc rs cs rd wr data dval t dsp p addr rd data terrpt addr decoder wr f ad p o ad p t ad t dsp a ad t a ad dsp a o t p rd wr cs rs d d d rs ad w rs d rs s wr rs rs s t t r w rd wr p rp w w r rr
rev. 0 e22e AD7725 the status register the status register is a 16-bit register that provides the user with information about the status of the device. the information avail- able to the user includes whether a configuration file was loaded successfully, what errors occurred if any, the last instruction written, and other information that may be useful to the user when operating the device. to read the status register, rs is taken high and rd/ wr w cs t t t t s r f s t d r t r d d r t w d d e t d v crc e t d e t r r r r r r r r r r r r r r r r r r cfged c e f t t s p c d rd r d d rcov d r c d w ad aort wc w c d wce a w c d e aort a t fr ro c d f ad t ad t wc w c w t cs t d s r wc e w c e w t t
rev. 0 AD7725 e23e converting to begin conversions, the rdconv (read converter data) instruction is issued (see table iii). int is asserted as soon as the conversion data is ready to be read (bit 14 of the status register will be set). int remains high until the digital word is read from the device. it will then go low and return high when the next conversion is complete. the device continues to con- vert until the abort instruction is issued. serial mode the serial mode is selected by tying s/ p dv dd f ad t ad fs sd fso sdo sco d sco t fs fso t ad t cft sco eft sco p ad s s t sode sode t v t dsp t dsp epro t epro ro fr t ro s ad epro dsp dsp dsp l c d dsp dsp t dsp ad t sode dv dd sode dgd t ad dsp t fs sd sco f soe dsp cfged f cfged t t err cfged t t t resetcfg w soe t ad t sco scr cl s cr cl scr sco cl ad cl f t ad fs cl ad t scl fs f ad dsp f dv dd soe err dval s p t resetcfg cfged sode sc sco fso sdo sd fs ad scl rfs dr dt tfs adsp sode t dv dd f c d l f c d dsp p ower o reset edate oot fro a dsp serdefed flter data loaded to te postprocessor fro a dsp cfged t devce starts covertg sode sode data loaded correctl plse resetcfg low o es err soe goes g f f c dsp epro l c d e epro
rev. 0 e24e AD7725 table iv. programming modes s/ p pr p rw r r pr p p pr prpr pr prpr pr pr p pr soe epro t ad sco d sco cl fs o soe epro sco cl cl scr cfged t err cfged t resetcfg w soe epro f ad epro f dv dd err dval s p t resetcfg cfged sode sc sco fso sdo fs ad scl rfs dr adsp sode ce oe ceo data cl seral epro dv dd sd f c d l f c d e epro p ower o reset edate oot fro a epro serdefed flter data loaded to te postprocessor fro epro soe goes g cfged t devce starts covertg sode sode data loaded correctl plse resetcfg low o es err soe goes low f f c epro ro fr d f t ad sode sode dgd t ad ro t o cfged f cfged t t ad fs sd dgd ad adc d sco cl o sco scr cl cl a sco cft w scr sco cl w scr sco cl w cft sco cft f ad f
rev. 0 AD7725 e25e dv dd soe err dval s/ p init resetcfg cfgend smode0 smode1 sync sco fso sdo sdi fsi AD7725 sclk0 rfs0 dr0 dt0 tfs0 adsp-21xx figure 30. connection diagram for loading the default filter in bfr mode p ower on reset immediate boot from rom default filter loaded into postprocessor from internal rom cfgend = 1 init = 1 device starts converting smode0 = 0 smode1 = 0 figure 31. flow chart of bfr mode daisy-chaining devices several AD7725s can be daisy-chained/cascaded together. this feature of the AD7725 reduces system demands as it allows several devices to be configured using one serial data stream. it also allows conversion data from several devices to be read back by a single dsp as one serial data stream. when devices are daisy-chained, configuration/conversion data flows from device to device using the sdo/fso and sdi/fsi pins of each device. a specific daisy-chaining configuration file needs to be devel- oped using the filter design package filter wizard. there are a few different daisy-chaining options for the user to choose from: (i) daisy-chaining during configuration several AD7725s can be daisy-chained together so that they can all be configured from a common external serial eprom or a dsp. filter wizard allows the user to specify the number of devices in the chain and to design a specific filter for each device. it then generates a separate configura- tion file for each device. the configuration files for all the devices can be combined into one configuration file (in order, starting with the file for the first device), e.g., with a text editor, so that the user only has to load one file into the eprom or dsp. this configuration file is loaded into the devices using the fsi/sdi and the fso/sdo of each device. once the devices have been configured in a daisy chain, each device can be run independently and conver- sion data is read back using the fso and sdo from each device separately. (ii) daisy-chaining?onfiguration and conversion data several AD7725s can be daisy-chained so that they are configured from a common external serial eprom or dsp (as discussed in (i) above) and all conversion data from each individual device can be read back by a single dsp on one serial data stream. to do this, an interlacer is required following each filter on each device. this design can be im plemented using filter wizard. the function of the interlacer is to sequentially combine the conversion data outputs of each device into one serial data stream. the interlacer combines the data using interpolation and summing. interpolation pads the data with zeros; then the interlacer takes the output data from the previous device, delays it by one clock cycle and sums it with the interpolated output from the current device. this occurs on each device in the chain and the output data from the last device consists of all the devices conversion data in one continuous data stream. when design- ing filters with interlacing, the decimation rate of the filter on each device should be twice the number of devices in the chain, or a multiple of this value, to ensure there is no inter- ference between the conversion data of different devices. due to the interpolation and decimation, the effective output data rate of each device (out of the last device) is cl kin/(16 loading configuration data when loading the configuration file from a common eprom or dsp, the configuration data is loaded into the first device in the chain. once this device is configured, the data will be loaded into the second device in the chain via fso/sdo of device 1 and fsi/sdi of device 2. when this device is configured, the data is loaded into the next device in the chain until all de vices are configured. the cfgend pin of the last device is con nected to the init pin of all the devices so that when the last device is successfully configured, conversions are initiated. device1 device3 device2 analog input analog input analog input filter1 dec 6 filter2 dec 6 filter3 dec 6 d igital in d igital in interlacer interlacer interlacer da ta output format: d evice3, device2, d evice1; device3, ... clkin 9.6mhz e ffective data output rate f rom each device: = clkin/(16 3) = 200ksps data output rate = clkin/16 figure 32. daisy-chaining example
rev. 0 e26e AD7725 converting when the adcs are converting, the conversion result of the first device in the chain is sent to the second device and is com- bined with the conversion data of the second device by the interlacer. this data is then combined with the data from the next device in the chain, and so on. the output from the last device will be a continuous serial data stream consisting of the conversion results of all the devices in the chain. a single dsp can read back all the conversion data in the sequence: device n; ... device 2; device 1; device n; ... device 2; device 1; and so on. figure 33 shows a connection diagram for daisy-chaining multiple devices with a common dsp, and figure 34 shows a connection diagram for daisy-chaining multiple devices with a common dsp and a shared eprom. AD7725 sdi fsi fso sdo cfgend init dsp mode so e sco AD7725 adsp-21xx sclk0 rfs0 dr0 dt0 tfs0 irq1 fso sdo sdi fsi cfgend init sport0 dsp mode so e sco figure 33. daisy-chaining devices with a common dsp xc1700d clk ceo dat oe ce AD7725 AD7725 fso sdo sdi fsi sdi fsi fso sdo cfgend init cfgend init eprom mode dsp mode soe sco sco adsp-21xx sclk0 rfs0 dr0 sport0 soe figure 34. daisy-chaining devices with a common dsp and a shared eprom (iii) cascading filters across multiple devices if the design of your filter is too large for one AD7725 device to handle, the filter can be cascaded across multiple devices. for example, if you have a 3-stage filter in your design that requires over 108 taps to be implemented, this filter can be shared between two or three devices. to do this, a configuration file needs to be developed in filter wizard. filter wizard allows the user to split the filter stages up and implement them on different devices with the output of the final device being the filtered input of the first device. serial interface to a dsp in serial mode, the AD7725 can be directly interfaced to sev- eral industry-standard digital signal processors. in all cases, the AD7725 operates as the master with the dsp operating as a slave. the AD7725 provides its own serial clock (sco) to trans- mit the digital words on the sdo pin to the dsp. the AD7725 also generates the frame synchronization signal that synchronizes the transfer of the 16-bit word from the AD7725 to a dsp. sco will have a frequency equal to clkin or clkin/2 depending on the state of the scr pin. AD7725 to adsp-21xx interface figure 35 shows the interface between the adsp-21xx and the AD7725. for the adsp-21xx, the bits in the serial port control register should be set up as rfsr and tfsr = 1 (a frame sync is required for each data transfer), slen = 15 (16-bit word lengths), rfsw and tfsw = 0 (normal framing mode for receive and transmit operations), invrfs and invtfs = 0 (active high rfs and tfs), irfs = 0 (external rfs), itfs = 1 (internal tfs), and isclk = 0 (external serial clock). AD7725 * sco fso sclk dr rfs tfs adsp-21xx * * additional pins omitted for clarity sdo sdi fsi dt figure 35. AD7725 to adsp-21xx interface grounding and layout the analog and digital power supplies to the AD7725 are inde- pendent and separately pinned out to minimize coupling between analog and digital sections within the device. all the AD7725 agnd and dgnd pins should be soldered directly to a ground plane to minimize series inductance. in addition, the ac path from any supply pin or reference pin (ref1 and ref2) through its decoupling capacitors to its associated ground must be made as short as possible (figure 36). to achieve the best decoupling, place surface mount capacitors as close as possible to the device, ideally right up against the device pins. to avoid capacitive coupling, ground planes must not overlap. the AD7725?s digital and analog ground planes must be con- nected at one place by a low inductance path, preferably right under the device. typically, this connection will either be a trace on the printed circuit board of 0.5 cm wide when the ground planes are on the same layer, or 0.5 cm wide minimum plated through holes when the ground planes are on different layers. any external logic connected to the AD7725 should use a ground plane separate from the AD7725?s digital ground plane. these two digital ground planes should also be con- nected at just one place. separate power supplies for av dd and dv dd are also highly desirable. the digital supply pin dv dd should be powered from a separate analog supply, but if necessary dv dd may share its power connection to av dd .
rev. 0 AD7725 e27e a minimum etch technique is generally best for ground planes as it gives the best shielding. noise can be minimized by paying attention to the system layout and preventing different signals from interfering with each other. high level analog signals should be separated from low level analog signals, and both should be kept away from digital signals. in waveform sampling and recon- struction systems, the sampling clock (clkin) is as vulnerable to noise as any analog signal. clkin should be isolated from the analog and digital systems. fast switching signals like clocks should be shielded with their associated ground to avoid radiating noise to other sections of the board, and clock signals should never be routed near the analog inputs. avoid running digital lines under the device, as these will couple noise onto the die. the analog ground plane should be allowed to run under the AD7725 to shield it from noise coupling. the power supply lines to the AD7725 should use as large a trace as possible (preferably a plane) to provide a low impedance path and reduce the effects of glitches on the power supply line. avoid crossover of digital and analog signals. traces on oppo- site sides of the board should run at right angles to each other. this will reduce the effects of feedthrough through the board. 0.1 f av dd a gnd 10nf dv dd dgnd dgnd 5v dgnd 10 f + 10nf 10nf 10nf av dd 1 a gnd1 a gnd1 av dd a gnd 10nf a gnd 0.1 f 0.1 f 10 f 5v a gnd ref2 ref1 a gnd2 220nf 10nf 1 f analog ground plane digital ground plane 39 figure 36. reference and supply decoupling optimizing heat removal by pcb construction and device mounting for normal still air conditions, the primary heat dissipation path from the chip to the ambient is via the component leads into the pcb. the thermal resistance of the board is then a significant variable. this can be lowered by maximizing the use of ground planes as heat sinks and also by optimizing the way in which the heat can be dissipated, for example conduction into the board mounting chassis. the greater the percentage of copper in the board, especially in the region of the device, the lower the ther- mal resistance. the use of wide tracks and thermal vias to the ground plane will have a significant effect. placing critical com- ponents close to where the edge of the board is attached to the chassis can provide additional cooling without the use of heat sinks or forced air. avoid close spacing of high power devices in order to ensure that the heat is dissipated over the maximum possible area. evaluating the AD7725 performance there is an AD7725 evaluation package available that includes a fully assembled tested evaluation board, documenta- tion, and software for controlling the board from a pc via the evaluation board controller. the evaluation board controller can be used in conjunction with the AD7725 evaluation board (as well as with many other analog devices evaluation boards ending in the cb designator) to demonstrate/evaluate the per- formance of the AD7725. the software allows the user to perform ac (fast fourier transform) and dc (histogram of codes) tests on the AD7725. by downloading the filter design package, filter wizard, user-defined filter files can be loaded into the AD7725 to program the postprocessor via the evaluation board controller. see the adi website for more information.
?8 c01552??/03(0) printed in u.s.a. outline dimensions 44-lead plastic quad flatpack [mqfp] (s-44) dimensions shown in millimeters 13.20 bsc sq 0.80 bsc 10.00 bsc sq 0.45 0.29 2.20 2.00 1.80 2.45 max 1.03 0.88 0.73 8 0.8 seating plane top view (pins down) 1 33 34 11 12 23 22 44 coplanarity 0.10 compliant to jedec standards ms-022-ab pin 1 0.25 max

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